This work describes a methodology to model power consumption of logic modules. A detailed mathematical model is presented\r\nand incorporated in a tool for translation of models written in VHDL to SystemC. The functionality for implicit power monitoring\r\nand estimation is inserted at module translation. The translation further implements an approach to wrap RTL to TLM interfaces\r\nso that the translated module can be connected to a system-level simulator. The power analysis is based on a statistical model of\r\nthe underlying HW structure and an analysis of input data. The flexibility of the C++ syntax is exploited, to integrate the power\r\nevaluation technique. The accuracy and speed-up of the approach are illustrated and compared to a conventional power analysis\r\nflow using PPR simulation, based on Xilinx technology.
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